Wait Construct




Verilog HDL Testbench Constructs


This is a reference of Verilog HDL constructs and commands for creating testbenches for HDL modules used in FPGA's and CPLD's.

Command Index


Real ECG

Event Control Contsruct

Event control is initiated by the @ symbol, followed by the sensitivity list. In a test bench, execution is suspended until one of the events in the sensitivity list occurs. This is typically used for edge transitions.

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Wait Construct

The wait statement is similar to event control. Event control is typically used for waiting for edge transitions; the wait statement is typically used for conditions that indicate level transitions.

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Timescale Directive

`timescale [time unit] / [time precision]

The Timescale directive is one of many compiler directives. Compiler directives are preceded by the backwards quote (` ), which usually shares the same key as the tilda (~) symbol on the upper left corner of the keyboard.

The timescale directive specifies the default time unit used for the simulation. In this case, it is 1ns, with a precision of 1 ps (.001ns):

`timescale 1 ns / 1 ps

When a delay is specified in the simulation, the delay is multiplied by the [time unit]:

// 20 nS delay given timescale shown above
#20 q = a & b;

So in the example above, the delay would be (20 * 1 nS), or 20 nS. The [time precision] is only important when a time delay with a decimal fraction is used. Given the following time delay:

// 20.005 nS delay given timescale shown above
#20.0053 q = a & b;

The time is rounded to 20.005 nS becouse the resolution is only to .001 nS or 1 pS.

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System Functions

The predefined system functions in Verilog are preceded by the dollar sign ($).

  • $unsigned : Convert a reg or wire data type to the unsigned type.
  • $signed : Convert a reg or wire data type to the signed type.
  • $time : Returns the simulation time as a 64 bit integer.
  • $stime : Returns the simulation time as a 32 bit integer.
  • $realtime : Returns the simulation time as a real number.
  • $timeformat(time unit, precision number, suffix string, minimum field width) : An example would be:

    $timeformat(-9, 1, "ns", 12);

    The time unit number code is associated with the actual time unit as follows:
    • 0 -> 1 S
    • -1 -> 100 mS
    • -2 -> 10 mS
    • -3 -> 1 mS
    • -4 -> 100 uS
    • -5 -> 10 uS
    • -6 -> 1 uS
    • -7 -> 100 nS
    • -8 -> 10 nS
    • -9 -> 1 nS
    • -10 -> 100 pS
    • -11 -> 10 pS
    • -12 -> 1 pS
    • -13 -> 100 fS
    • -14 -> 10 fS
    • -15 -> 1 fS
  • $finish : Terminates the simulation, and exits the simulation program.
  • $stop : Suspends the simulation, but stays in the simulation program so that the waveform can be examined.
  • $display : Similar syntax as sprintf() in C/C++. Supports %d as an integer number, and %b as a binary number. $time is often used with %d as the first field to show the simulation time. $display automatically adds a newline.
  • $write : Same as $display, but does not add a newline. A "\n" must be added if a newline is desired.
  • $strobe : Similar to $display, but is executed at the end of the current simulation time step. It helps to avoid mismatched data due to race conditions.
  • $monitor : Unlike the $display, $write, and $strobe functions, which are executed only once when they are called, the $monitor function displays text when any of its arguments change value.

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(1) Verilog Altera

(2) System Verilog

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